The present invention relates to semiconductor memory devices and methods for fabricating the semiconductor memory devices and, more particularly, to semiconductor memory devices having a ferroelectric capacitive element and fabrication methods therefor.
Hitherto, semiconductor memory devices, in particular, nonvolatile memory devices using ferroelectrics have been proposed. As one of information retaining methods therefor, there has been available a method in which electric charges are retained at the gate electrode of a field-effect transistor.
With reference to FIGS. 7A to 7F, below described is a semiconductor memory device of the prior art using the method in which electric charges are retained to the gate electrode of a field-effect transistor as described in Japanese Patent Laid-Open Publication HEI 8-55918. FIGS. 7A to 7F are fabrication process diagrams of a semiconductor memory device of the prior art using the method in which electric charges are retained at the gate electrode of a field-effect transistor.
First, as shown in FIG. 7A, a trench 22 is formed in a p-type semiconductor substrate 21 by lithography and etching. Then, as shown in FIG. 7B, silicon oxide 23 is buried into the trench 22. Then, into the semiconductor substrate 21 is ion-implanted an n-type dopant that makes the semiconductor substrate 21 into a conductive type opposite to that of the semiconductor substrate, and subsequently high-temperature heat treatment is performed to thereby electrically activate the dopant, by which a source/drain region 24 is formed.
Next, as shown in FIG. 7C, by selectively removing the silicon oxide 23 buried into the trench 22, a trench is formed and thereafter silicon oxide 25, which is a low dielectric constant insulator, is deposited overall. Next, as shown in FIG. 7D, Bi4Ti3O12 is sputtered and deposited in the trench as a ferroelectric film 26, and buried by etchback.
Next, as shown in FIG. 7E, Pt is deposited on the ferroelectric film 26 as a gate electrode 27. As the method for burying the ferroelectric film 26 in the trench 22, it is also possible to perform mechanical polishing, chemical polishing or mechanical-chemical polishing after the deposition of the ferroelectric film. Finally, as shown in FIG. 7F, interconnections of metallic source/drain electrodes 28 are implemented, thus completing the process.
By using the above method, because the source/drain region is formed before the formation of the ferroelectric film, constituent elements of the ferroelectric film can be prevented from being diffused in the semiconductor substrate due to the heat treatment for the formation of the source/drain region. Also, since the ferroelectric film can be formed in self alignment to the source/drain region, it becomes possible to realize a highly integrated nonvolatile memory device in which device dimensions have been scaled down.
However, with the use of the above-described process, there is a disadvantage that since peripheral portions of the trench are damaged during the formation of the trench in the semiconductor substrate by etching, transistor characteristics would be deteriorated. Further, since the interface between the gate ferroelectric film and the semiconductor substrate is located lower than the surface of the source/drain region, a horizontal electric field is applied to the gate ferroelectric film by the bias between the source and drain regions, so that vertical components of spontaneous polarization would lower, as a further disadvantage.
An object of the present invention is to provide a semiconductor memory device and a fabrication method therefor without the above technical disadvantages, which makes it possible to form the source/drain region before the gate formation and to form the gate ferroelectric film in self alignment to the source/drain region.
In order to achieve the above object, according to the present invention, there is provided a semiconductor memory device comprising: a semiconductor substrate of a first conductive type; a source/drain region of a second conductive type opposite to the first conductive type formed in the semiconductor substrate; an interlayer insulator formed on the semiconductor substrate; a trench formed in the interlayer insulator in self alignment to the source/drain region, the trench extending so as to reach a surface of the semiconductor substrate; and a gate formed at least on an inner wall of the trench.
In an embodiment of the semiconductor memory device, the gate has a lamination structure of the gate ferroelectric film and the gate electrode in this order from the semiconductor substrate side.
In an embodiment of the semiconductor memory device, a gate buffer dielectric film is provided between the gate ferroelectric film and the semiconductor substrate.
The present invention also provides a method for fabricating a semiconductor memory device, comprising: a step of forming a dummy gate electrode material on an overall surface of a semiconductor substrate of a first conductive type; a step of forming a dummy gate electrode just above a channel formation region of the semiconductor substrate by patterning the dummy gate electrode material; a step of forming a source/drain region of a second conductive type opposite to the first conductive type in self alignment to the dummy gate electrode by ion-implanting a dopant of the second conductive type with the dummy gate electrode used as a dopant implantation mask and thereafter performing heat treatment to thereby activate the dopant; a step of forming an interlayer insulator overall to coat the dummy gate electrode therewith; a step of exposing a top surface of the dummy gate electrode by subjecting the interlayer insulator to a planarization process; a step of forming in the interlayer insulator a trench that reaches a semiconductor substrate surface in self alignment to the source/drain region by selectively removing only the dummy gate electrode; a step of burying a gate electrode material and a ferroelectric film into the trench by forming overall the ferroelectric film and the gate electrode material sequentially in this order; and a step of forming a gate comprising a gate electrode and a gate ferroelectric film in self alignment to the source/drain region by patterning the gate electrode material and the ferroelectric film.
According to the above invention, since the ferroelectric film is formed in self alignment to the source/drain region, when a multiplicity of devices are formed on a semiconductor substrate, the characteristics of the devices shows less variations. Also, because heat is not applied to the ferroelectric film, structural deformations such as cracks are not observed in the ferroelectric film even after the completion of the process. Furthermore, according to a dopant analysis, neither diffusion of ferroelectric material elements into the substrate nor increase in the leak current is not observed.
Consequently, by forming the source/drain region before the gate formation, and by forming the gate ferroelectric film in self alignment to the source/drain region, activation of the dopant in the source/drain region and the assurance of film quality of the ferroelectric film can be achieved at the same time, so that the transistor characteristics can be prevented from deterioration. Further, a highly integrated nonvolatile semiconductor memory device having scaled-down device dimensions and using ferroelectric film can be obtained.
In an embodiment of the method for fabricating a semiconductor memory device, the method for fabricating a semiconductor memory device further comprises: a step of burying a gate electrode material, a ferroelectric film and a buffer dielectric film into the trench by forming overall the buffer dielectric film, the ferroelectric film and the gate electrode material sequentially in this order after the formation of the trench; and a step of forming a gate comprising a gate electrode, a gate ferroelectric film and a gate buffer dielectric film in self alignment to the source/drain region by patterning the gate electrode material, the ferroelectric film and buffer dielectric film.
The present invention further provides a method for fabricating a semiconductor memory device, comprising: a step of forming a buffer dielectric film and a dummy gate electrode material sequentially in this order on an overall surface of a semiconductor substrate of a first conductive type; a step of forming a dummy gate electrode and a gate buffer dielectric film just above a channel formation region of the semiconductor substrate by patterning the dummy gate electrode material and the buffer dielectric film; a step of forming a source/drain region of a second conductive type opposite to the first conductive type in self alignment to the dummy gate electrode by ion-implanting a dopant of the second conductive type with the dummy gate electrode used as a dopant implantation mask and thereafter performing heat treatment to thereby activate the dopant; a step of forming an interlayer insulator overall to coat the dummy gate electrode; a step of exposing a top surface of the dummy gate electrode by subjecting the interlayer insulator to a planarization process; a step of forming in the interlayer insulator a trench that reaches a gate buffer dielectric film surface in self alignment to the source/drain region by selectively removing only the dummy gate electrode; a step of burying a gate electrode material and a ferroelectric film into the trench by forming overall the ferroelectric film and the gate electrode material sequentially in this order; and a step of forming a gate comprising a gate electrode, a gate ferroelectric film and the gate buffer dielectric film in self alignment to the source/drain region by patterning the gate electrode material and the ferroelectric film.
With adoption of this invention, the ferroelectric film can be formed with better alignment to the source/drain region.
In an embodiment of the method for fabricating a semiconductor memory device, the semiconductor substrate is a silicon substrate and the buffer dielectric film is formed of Bi2SiO5.
According to the above embodiment, when Bi2Ti3O12 is used for the ferroelectric film, a C-axis oriented Bi2Ti3O12 suitable for low voltage drive can be formed.
In an embodiment of the method for fabricating a semiconductor memory device, a surface of the interlayer insulator and the top surface of the dummy gate electrode are made into the same surface by performing the planarization process for the interlayer insulator by using chemical-mechanical polishing process.
According to the above embodiment, planarization of the semiconductor device can be achieved.
In an embodiment of the method for fabricating a semiconductor memory device, the surface of the interlayer insulator, the top surface of the dummy gate electrode and a surface of device-isolating field oxide are made into the same surface by performing the planarization process for the interlayer insulator by using chemical-mechanical polishing process.
According to the above embodiment, further planarization of the semiconductor device can be achieved.
The present invention still further provides a method for fabricating a semiconductor memory device, comprising: a step of forming, in a semiconductor substrate of a first conductive type, a dopant diffusion region of a second conductive type opposite to the first conductive type by ion-implanting a dopant of the second conductive type on an overall surface of the semiconductor substrate; a step of, after forming overall an interlayer insulator, forming in the interlayer insulator a trench that reaches a semiconductor substrate surface just above a channel formation region of the semiconductor substrate by patterning the interlayer insulator; a step of forming a source/drain region of the second conductive type in self alignment to the trench by ion-implanting a dopant of the first conductive type with the interlayer insulator used as a dopant implantation mask and thereafter performing heat treatment to thereby activate the dopant so that the dopant diffusion region of the second conductive type just under the trench is made into a dopant diffusion region of the first conductive type; a step of burying a gate electrode material and a ferroelectric film into the trench by forming overall the ferroelectric film and the gate electrode material sequentially in this order; and a step of forming a gate comprising a gate electrode and a gate ferroelectric film in self alignment to the source/drain region by patterning the gate electrode material and the ferroelectric film.
With adoption of this invention, since a ferroelectric film can be formed in self alignment to the source/drain region without the formation or removal of dummy gate electrode, the required man-hour of process can be reduced.
In an embodiment of the method for fabricating a semiconductor memory device, the heat treatment to thereby activate the dopant is performed after implanting the dopant of the second conductive type in the overall surface of the semiconductor substrate of the first conductive type.
In an embodiment of the method for fabricating a semiconductor memory device, there is provided the method for fabricating a semiconductor memory device, further comprising: a step of, subsequent to the step of making the dopant diffusion region of the second conductive type just under the trench into the dopant diffusion region of the first conductive type, burying the gate electrode material, a ferroelectric film and a buffer dielectric film into the trench by forming overall the buffer dielectric film, the ferroelectric film and the gate electrode material sequentially in this order; and a step of forming a gate comprising the gate electrode, the gate ferroelectric film and a gate buffer dielectric film in self alignment to the source/drain region by patterning the gate electrode material, the ferroelectric film and the buffer dielectric film.
In an embodiment of the method for fabricating a semiconductor memory device, the dummy gate electrode material is formed of silicon nitride and the interlayer insulator is formed of silicon oxide.
According to the above embodiment, in the process of planarization of the first interlayer insulator by CMP process, the dummy gate electrode fulfills the function as a stopper film successfully.